Messages in this thread | | | From | Ravi Bangoria <> | Subject | [PATCH 0/6] perf/amd: Zen4 IBS extensions support | Date | Mon, 25 Apr 2022 10:13:17 +0530 |
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IBS support has been enhanced with two new features in upcoming uarch: 1. DataSrc extension and 2. L3 Miss Filtering capability. Both are indicated by CPUID_Fn8000001B_EAX bit 11.
DataSrc extension provides additional data source details for tagged load/store operations. Add support for these new bits in perf report/ script raw-dump.
IBS L3 miss filtering works by tagging an instruction on IBS counter overflow and generating an NMI if the tagged instruction causes an L3 miss. Samples without an L3 miss are discarded and counter is reset with random value (between 1-15 for fetch pmu and 1-127 for op pmu). This helps in reducing sampling overhead when user is interested only in such samples. One of the use case of such filtered samples is to feed data to page-migration daemon in tiered memory systems.
Add support for L3 miss filtering in IBS driver via new pmu attribute "l3missonly". Example usage:
# perf record -a -e ibs_op/l3missonly=1/ --raw-samples sleep 5 # perf report -D
Some important points to keep in mind while using L3 miss filtering: 1. Hw internally reset sampling period when tagged instruction does not cause L3 miss. But there is no way to reconstruct aggregated sampling period when this happens. 2. L3 miss is not the actual event being counted. Rather, IBS will count fetch, cycles or uOps depending on the configuration. Thus sampling period have no direct connection to L3 misses.
1st causes sampling period skew. Thus, I've added warning message at perf record:
# perf record -c 10000 -C 0 -e ibs_op/l3missonly=1/ WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled and tagged operation does not cause L3 Miss. This causes sampling period skew.
User can configure smaller sampling period to get more samples while using l3missonly.
Ravi Bangoria (6): perf/amd/ibs: Add support for L3 miss filtering perf/amd/ibs: Advertise zen4_ibs_extensions as pmu capability attribute perf/tool/amd/ibs: Warn about sampling period skew perf/tool: Parse non-cpu pmu capabilities perf/tool/amd/ibs: Support new IBS bits in raw trace dump perf/tool/amd/ibs: Fix comment
arch/x86/events/amd/ibs.c | 76 +++++-- arch/x86/include/asm/amd-ibs.h | 18 +- arch/x86/include/asm/perf_event.h | 3 + tools/arch/x86/include/asm/amd-ibs.h | 18 +- .../Documentation/perf.data-file-format.txt | 18 ++ tools/perf/arch/x86/util/evsel.c | 31 +++ tools/perf/util/amd-sample-raw.c | 68 +++++- tools/perf/util/env.c | 48 +++- tools/perf/util/env.h | 11 + tools/perf/util/evsel.c | 7 + tools/perf/util/evsel.h | 1 + tools/perf/util/header.c | 211 ++++++++++++++++++ tools/perf/util/header.h | 1 + tools/perf/util/pmu.c | 15 +- tools/perf/util/pmu.h | 2 + 15 files changed, 483 insertions(+), 45 deletions(-)
-- 2.27.0
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