Messages in this thread | | | Date | Tue, 19 Apr 2022 15:06:54 +0300 | Subject | Re: [PATCH 0/2] Update register & interrupt info in am65x DSS | From | Tomi Valkeinen <> |
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On 19/04/2022 10:03, Aradhya Bhatia wrote: > The Display SubSystem IP on the ti's am65x soc has an additional > register space "common1" and services a maximum of 2 interrupts. > > The first patch in the series adds the required updates to the yaml > file. The second patch then reflects the yaml updates in the DSS DT > node of am65x soc. > > Aradhya Bhatia (2): > dt-bindings: display: ti,am65x-dss: Add missing register & interrupt > arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- > arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- > 2 files changed, 11 insertions(+), 5 deletions(-) >
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
How are you planning to use the common1 area?
Tomi
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