Messages in this thread | | | Date | Wed, 20 Apr 2022 10:05:34 +0300 | Subject | Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt | From | Tomi Valkeinen <> |
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Hi,
On 19/04/2022 17:20, Rob Herring wrote: > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: >> The DSS IP on the ti-am65x soc supports an additional register space, >> named "common1". Further. the IP services a maximum number of 2 >> interrupts. >> >> Add the missing register space "common1" and the additional interrupt. >> >> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> >> --- >> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- >> 1 file changed, 7 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index 5c7d2cbc4aac..102059e9e0d5 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -26,6 +26,7 @@ properties: >> Addresses to each DSS memory region described in the SoC's TRM. >> items: >> - description: common DSS register area >> + - description: common1 DSS register area > > You've just broken the ABI. > > New entries have to go on the end.
I'm curious, if the 'reg-names' is a required property, as it is here, does this still break the ABI?
Tomi
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