Messages in this thread | | | Date | Tue, 12 Apr 2022 23:17:50 +0100 (BST) | From | "Maciej W. Rozycki" <> | Subject | Re: [PATCH] x86/apic: Clarify i82489DX bit overlap in APIC_LVT0 |
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On Tue, 12 Apr 2022, Thomas Gleixner wrote:
> Daniel stumbled over the undocumented bit overlap of the i82498DX external > APIC and the TSC deadline timer configuration bit in modern APICs.
For the record, it's documented in the i82498DX datasheet[1] and user manual[2]:
'Bits [19:18] Timer Base: This field selects the time base input to be used by the timer.
00: (Base 0): Uses "CLKIN" as input.
01: (Base 1): Uses "TMBASE".
10: (Base 2): Uses the output of the divider (Base 2).'
(the wording is virtually the same in both sources). Base 2 setting is compatible with later APIC implementations.
Since you're removing the macros and the documents referred aren't easily available it may be worth to mention the settings somewhere, such as the comment you're adding.
Intel indeed did not document the two-bit field in any later literature, and the i82498DX part cannot be used with any other APIC device due to a protocol (and also wiring) difference in the inter-APIC communication bus.
There's also bit 2 of the Divide Configuration Register. That bit is hardwired to 0 in later APIC versions, however in the i82498DX it selects the time base input to be used by the divider, 0 for CLK (CLKIN) or 1 for TMBASE. Conversely bit 3 is hardwired to 0 in the i82498DX.
References:
[1] "82489DX Advanced Programmable Interrupt Controller", Intel Corporation, Order Number: 290446-002, October 1993, Section 6.12 "Timer Registers", p.27
[2] M. Jayakumar, "AP-388 82489DX User's Manual", Multiprocessor Technology Group, Intel Corporation, Order Number: 292116-002, November 1995, Section "Register Programming Details", p.22
FWIW,
Maciej
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