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Subject[PATCH 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
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Add description to support Axis, ARTPEC-8 SoC.

ARTPEC-8 is the SoC platform of Axis Communications

and PCIe phy is designed based on SAMSUNG PHY.



Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>

---

.../bindings/phy/axis,artpec8-pcie-phy.yaml | 67 ++++++++++++++++++++++

1 file changed, 67 insertions(+)

create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml



diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml

new file mode 100644

index 0000000..f5f4166

--- /dev/null

+++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

+%YAML 1.2

+---

+$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml#

+$schema: http://devicetree.org/meta-schemas/core.yaml#

+

+title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings

+

+maintainers:

+ - Jesper Nilsson <jesper.nilsson@axis.com>

+

+properties:

+ compatible:

+ const: axis,artpec8-pcie-phy

+

+ reg:

+ items:

+ - description: PHY registers.

+ - description: PHY coding sublayer registers.

+

+ reg-names:

+ items:

+ - const: phy

+ - const: pcs

+

+ clocks:

+ items:

+ - description: PCIe PHY reference clock

+

+ clock-names:

+ items:

+ - const: ref_clk

+

+required:

+ - compatible

+ - "#phy-cells"

+ - reg

+ - reg-names

+ - clocks

+ - clock-names

+ - samsung,fsys-sysreg

+ - num-lanes

+

+

+additionalProperties: false

+

+examples:

+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>

+ #include <dt-bindings/interrupt-controller/arm-gic.h>

+

+ artec8 {
+ #address-cells = <2>;

+ #size-cells = <2>;

+ pcie_phy: pcie-phy@16c80000 {
+ compatible = "samsung,artpec8-pcie-phy";

+ #phy-cells = <0>;

+ reg = <0x0 0x16c80000 0x0 0x2000>,
+ <0x0 0x16c90000 0x0 0x1000>;
+ reg-names = "phy", "pcs";

+ clocks = <&clock_cmu_fsys 53>;

+ clock-names = "ref_clk";

+ samsung,fsys-sysreg = <&syscon_fsys>;

+ num-lanes = <2>;

+ };
+ };
+...

--

2.9.5

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