Messages in this thread | | | From | Bhupesh Sharma <> | Date | Thu, 24 Mar 2022 01:56:35 +0530 | Subject | Re: [PATCH v3 2/2] arm64: dts: qcom: sm8150: Add ufs power-domain entries |
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Hi Bjorn,
On Wed, 9 Mar 2022 at 04:35, Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > On Thu 03 Mar 02:21 CST 2022, Bhupesh Sharma wrote: > > > Add power-domain entries for UFS controller & phy nodes > > in sm8150 dts. > > > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > > Cc: Rob Herring <robh@kernel.org> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > index 6012322a5984..7aa879eb24d7 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > > @@ -1637,6 +1637,8 @@ ufs_mem_hc: ufshc@1d84000 { > > phy-names = "ufsphy"; > > lanes-per-direction = <2>; > > #reset-cells = <1>; > > + > > + power-domains = <&gcc UFS_PHY_GDSC>; > > It seems odd that the controller would be in the PHY power-domain?
Ok.
> > resets = <&gcc GCC_UFS_PHY_BCR>; > > reset-names = "rst"; > > > > @@ -1687,6 +1689,9 @@ ufs_mem_phy: phy@1d87000 { > > clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, > > <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > > > > + power-domains = <&gcc UFS_CARD_GDSC>, > > + <&gcc UFS_PHY_GDSC>; > > And "card" is typically related to the second UFS interface, so I > suspect you only would need the last one of these?
Right, I will send a fixed v4 version shortly.
Thanks, Bhupesh
> > + power-domain-names = "ufs_card_gdsc", "ufs_phy_gdsc"; > > resets = <&ufs_mem_hc 0>; > > reset-names = "ufsphy"; > > status = "disabled"; > > -- > > 2.35.1 > >
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