| Date | Wed, 23 Mar 2022 18:24:03 +0100 | Subject | Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node | From | Matthias Brugger <> |
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On 18/03/2022 15:45, Allen-KH Cheng wrote: > Add gce node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 0f9f211ca986..9e1b563bebab 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -6,6 +6,7 @@ > > /dts-v1/; > #include <dt-bindings/clock/mt8192-clk.h> > +#include <dt-bindings/gce/mt8192-gce.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h> > @@ -552,6 +553,15 @@ > #size-cells = <0>; > }; > > + gce: mailbox@10228000 { > + compatible = "mediatek,mt8192-gce"; > + reg = <0 0x10228000 0 0x4000>; > + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; > + #mbox-cells = <3>;
#mbox-cells should be 2, right?
Regards, Matthias
> + clocks = <&infracfg CLK_INFRA_GCE>; > + clock-names = "gce"; > + }; > + > scp_adsp: clock-controller@10720000 { > compatible = "mediatek,mt8192-scp_adsp"; > reg = <0 0x10720000 0 0x1000>;
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