Messages in this thread Patch in this message | | | Date | Mon, 21 Mar 2022 09:31:39 +0000 | From | Marc Zyngier <> | Subject | Re: [PATCH 2/3] irqchip/gic-v3: Detect LPI invalidation MMIO registers |
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On Thu, 17 Mar 2022 17:35:23 +0000, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote: > > On Tue, Mar 15, 2022 at 04:50:33PM +0000, Marc Zyngier wrote: > > Since GICv4.1, an implementation can offer the same MMIO-based > > implementation as DirectLPI, only with an ITS. Given that this > > can be hugely beneficial for workloads that are very LPI masking > > heavy (although these workloads are admitedly a bit odd). > > > > Interestingly, this is independent of RVPEI, which only *implies* > > the functionnality. > > > > So let's detect whether the implementation has GICR_CTLR.IR set, > > and propagate this as DirectLPI to the ITS driver. > > > > Signed-off-by: Marc Zyngier <maz@kernel.org> > > --- > > drivers/irqchip/irq-gic-v3.c | 15 +++++++++++---- > > include/linux/irqchip/arm-gic-v3.h | 2 ++ > > 2 files changed, 13 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > > index 736163d36b13..363bfe172033 100644 > > --- a/drivers/irqchip/irq-gic-v3.c > > +++ b/drivers/irqchip/irq-gic-v3.c > > @@ -918,7 +918,11 @@ static int gic_populate_rdist(void) > > static int __gic_update_rdist_properties(struct redist_region *region, > > void __iomem *ptr) > > { > > - u64 typer = gic_read_typer(ptr + GICR_TYPER); > > + u64 typer; > > + u32 ctlr; > > + > > + typer = gic_read_typer(ptr + GICR_TYPER); > > + ctlr = readl_relaxed(ptr + GICR_CTLR); > > > > /* Boot-time cleanip */ > > if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) { > > @@ -941,6 +945,7 @@ static int __gic_update_rdist_properties(struct redist_region *region, > > /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ > > gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); > > gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | > > + !!(ctlr & GICR_CTLR_IR) | > > gic_data.rdists.has_rvpeid); > > gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); > > > > @@ -962,7 +967,11 @@ static void gic_update_rdist_properties(void) > > gic_iterate_rdists(__gic_update_rdist_properties); > > if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) > > gic_data.ppi_nr = 0; > > - pr_info("%d PPIs implemented\n", gic_data.ppi_nr); > > + pr_info("GICv3 features: %d PPIs, %s%s\n", > > + gic_data.ppi_nr, > > + gic_data.has_rss ? "RSS " : "", > > + gic_data.rdists.has_direct_lpi ? "DirectLPI " : ""); > > I understand GICR_CTLR.IR detection (which is v4.1 feature) - I don't
No, it is *also* a GICv3 feature. RVPEI implies IR, but IR is a feature on its own (see my reply to Andre on the same subject). Nothing restrict IR to a GICv4.1+ implementation, and KVM is about to expose these registers to the GICv*3* guest.
> get why in this patch we are adding a GICv3 DirectLPI info dump (hunk > above), it is probably nitpicking but the hunk above does not seem to > belong in this patch - it is a separate print info refactoring or I am > reading it wrongly.
It is indeed just refactoring the kernel messages so that we can see that we enable DirectLPI for GICv3 as well. I honestly don't think this deserves a separate patch.
Thanks,
M.
-- Without deviation from the norm, progress is not possible.
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