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SubjectRe: [PATCH 2/3] irqchip/gic-v3: Detect LPI invalidation MMIO registers
On 2022-03-15 16:50, Marc Zyngier wrote:
> diff --git a/include/linux/irqchip/arm-gic-v3.h
> b/include/linux/irqchip/arm-gic-v3.h
> index 12d91f0dedf9..aeb8ced53880 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -127,6 +127,8 @@
> #define GICR_PIDR2 GICD_PIDR2
>
> #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
> +#define GICR_CTLR_IR (1UL << 1)
> +#define GICR_CTLR_CES (1UL << 2)
> #define GICR_CTLR_RWP (1UL << 3)
>
> #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)

As Oliver pointed out in [1], this is bollocks, and the two
new bits are swapped. I've now fixed that locally.

Thanks,

M.

[1] https://lore.kernel.org/r/YjEeNThfYFtTffWz@google.com
--
Jazz is not dead. It just smells funny...

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