Messages in this thread Patch in this message | | | From | Adam Ford <> | Subject | [PATCH] clk: vc5: Enable VC5_HAS_PFD_FREQ_DBL on 5p49v6965 | Date | Sun, 13 Mar 2022 06:57:04 -0500 |
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The 5p49v6965 has a reference clock frequency doubler. Enabling it adds versaclock_som.dbl to the clock tree, but the output frequency remains correct.
Suggested-by: Claude Fillion <Claude.Fillion@mksinst.com> Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index e7be3e54b9be..4d190579e874 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -1211,7 +1211,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = { .model = IDT_VC6_5P49V6965, .clk_fod_cnt = 4, .clk_out_cnt = 5, - .flags = VC5_HAS_BYPASS_SYNC_BIT, + .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_PFD_FREQ_DBL, }; static const struct i2c_device_id vc5_id[] = { -- 2.34.1
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