Messages in this thread | | | From | Bharat Kumar Gogada <> | Subject | [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port | Date | Mon, 7 Feb 2022 09:42:47 +0530 |
| |
Xilinx Versal Premium series has CPM5 block which supports Root port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additonal register bit to enable and handle legacy interrupts.
Bharat Kumar Gogada (2): PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver
.../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++- 2 files changed, 72 insertions(+), 8 deletions(-)
-- 2.17.1
| |