Messages in this thread | | | Subject | Re: [PATCH v2 7/7] irqchip/apple-aic: Add support for AICv2 | From | Hector Martin <> | Date | Sat, 26 Feb 2022 07:05:26 +0900 |
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On 26/02/2022 00.27, Marc Zyngier wrote: > On Thu, 24 Feb 2022 13:07:41 +0000, > Hector Martin <marcan@marcan.st> wrote: >> - /* >> - * Make sure the kernel's idea of logical CPU order is the same as AIC's >> - * If we ever end up with a mismatch here, we will have to introduce >> - * a mapping table similar to what other irqchip drivers do. >> - */ >> - WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id()); >> + if (aic_irqc->info.version == 1) { >> + /* >> + * Make sure the kernel's idea of logical CPU order is the same as AIC's >> + * If we ever end up with a mismatch here, we will have to introduce >> + * a mapping table similar to what other irqchip drivers do. >> + */ >> + WARN_ON(aic_ic_read(aic_irqc, AIC_WHOAMI) != smp_processor_id()); > > Don't you have a similar issue with AICv2? Or is it that AICv2 > doesn't have this register?
No concept of individual CPUs in AICv2 at all, so no WHOAMI register either :)
-- Hector Martin (marcan@marcan.st) Public Key: https://mrcn.st/pub
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