Messages in this thread Patch in this message | | | From | Carlos Bilbao <> | Subject | [PATCH] x86/mce: Simplify CPU vendor checks for AMD/Hygon and Intel/Zhaoxin | Date | Tue, 22 Feb 2022 09:58:58 -0600 |
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In a number of places across the MCE subsystem we check if we are running an x86 processor from AMD/Hygon or Intel/Zhaoxin vendors. Simplify these checks with two mce_flags updated at CPU MCE initialization.
Signed-off-by: Carlos Bilbao <carlos.bilbao@amd.com> --- arch/x86/kernel/cpu/mce/core.c | 22 ++++++++-------------- arch/x86/kernel/cpu/mce/intel.c | 3 +-- arch/x86/kernel/cpu/mce/internal.h | 8 +++++++- arch/x86/kernel/cpu/mce/severity.c | 3 +-- 4 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 5818b837fd4d..d88c7ba7f67a 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -241,7 +241,7 @@ static void print_mce(struct mce *m) { __print_mce(m); - if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) + if (!mce_flags.amd_compatible) pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); } @@ -503,8 +503,7 @@ int mce_usable_address(struct mce *m) return 0; /* Checks after this one are Intel/Zhaoxin-specific: */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && - boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) + if (!mce_flags.intel_compatible) return 1; if (!(m->status & MCI_STATUS_MISCV)) @@ -562,10 +561,7 @@ static bool whole_page(struct mce *m) bool mce_is_correctable(struct mce *m) { - if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) - return false; - - if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) + if (mce_flags.amd_compatible && m->status & MCI_STATUS_DEFERRED) return false; if (m->status & MCI_STATUS_UC) @@ -1450,8 +1446,7 @@ noinstr void do_machine_check(struct pt_regs *regs) * Check if this MCE is signaled to only this logical processor, * on Intel, Zhaoxin only. */ - if (m.cpuvendor == X86_VENDOR_INTEL || - m.cpuvendor == X86_VENDOR_ZHAOXIN) + if (mce_flags.intel_compatible) lmce = m.mcgstatus & MCG_STATUS_LMCES; /* @@ -1910,7 +1905,9 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); mce_flags.amd_threshold = 1; - } + mce_flags.amd_compatible = 1; + } else if (c->x86_vendor == X86_VENDOR_INTEL || c->x86_vendor == X86_VENDOR_ZHAOXIN) + mce_flags.intel_compatible = 1; } static void mce_centaur_feature_init(struct cpuinfo_x86 *c) @@ -2277,10 +2274,7 @@ static void vendor_disable_error_reporting(void) * the socket like the last level cache (LLC), the integrated memory * controller (iMC), etc. */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || - boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || - boot_cpu_data.x86_vendor == X86_VENDOR_AMD || - boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) + if (mce_flags.intel_compatible || mce_flags.amd_compatible) return; mce_disable_error_reporting(); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index bb9a46a804bf..169064fa12a9 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -85,8 +85,7 @@ static int cmci_supported(int *banks) * initialization is vendor keyed and this * makes sure none of the backdoors are entered otherwise. */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && - boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) + if (!mce_flags.intel_compatible) return 0; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 52c633950b38..562c768ceaf5 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -170,7 +170,13 @@ struct mce_vendor_flags { /* SandyBridge IFU quirk */ snb_ifu_quirk : 1, - __reserved_0 : 57; + /* CPUs are from AMD or Hygon */ + amd_compatible : 1, + + /* CPUs are from Intel or Zhaoxin */ + intel_compatible : 1, + + __reserved_0 : 55; }; extern struct mce_vendor_flags mce_flags; diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c index 7aa2bda93cbb..21aa31bd17a2 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -423,8 +423,7 @@ static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, int noinstr mce_severity(struct mce *m, struct pt_regs *regs, int tolerant, char **msg, bool is_excp) { - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || - boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) + if (mce_flags.amd_compatible) return mce_severity_amd(m, regs, tolerant, msg, is_excp); else return mce_severity_intel(m, regs, tolerant, msg, is_excp); -- 2.27.0
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