Messages in this thread | | | Subject | Re: [PATCH v10 02/18] clk: sunxi-ng: h616: Add PLL derived 32KHz clock | From | Samuel Holland <> | Date | Tue, 22 Feb 2022 21:28:25 -0600 |
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On 2/11/22 6:26 AM, Andre Przywara wrote: > The RTC section of the H616 manual mentions in a half-sentence the > existence of a clock "32K divided by PLL_PERI(2X)". This is used as > one of the possible inputs for the mux that selects the clock for the > 32 KHz fanout pad. On the H616 this is routed to pin PG10, and some > boards use that clock output to compensate for a missing 32KHz crystal. > On the OrangePi Zero2 this is for instance connected to the LPO pin of > the WiFi/BT chip. > The new RTC clock binding requires this clock to be named as one input > clock, so we need to expose this to the DT. In contrast to the D1 SoC > there does not seem to be a gate for this clock, so just use a fixed > divider clock, using a newly assigned clock number. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
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