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SubjectRe: [PATCH v2 17/23] arm64: dts: mt8192: Add vcodec lat and core nodes
On Fri, Feb 18, 2022 at 05:16:27PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 936aa788664f..543a80252ce5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1291,6 +1291,64 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec_dec@16000000 {

It's usually preferred to use '-' instead of '_' in the node name, like:

vcodec_dec: vcodec-dec@16000000 {

Same thing for the other vcodec nodes below.

But more importantly, the Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
dt-binding shows the mtk-vcodec-lat and mtk-vcodec-core as subnodes of
vcodec-dec. So I would follow that same structure here. Unless it does make more
sense to have the nodes separate like this, but in that case the dt-binding
should be updated.

> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + };
> +
> + vcodec_lat: vcodec_lat@0x16010000 {

Again, please drop the '0x' prefix.

> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec",
> + "vdec-top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec_core@0x16025000 {

Ditto.

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