Messages in this thread | | | From | Ard Biesheuvel <> | Date | Sun, 20 Feb 2022 14:30:24 +0100 | Subject | Re: [PATCH] irqchip/gic-v3: use dsb(ishst) to synchronize data to smp before issuing ipi |
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On Sat, 19 Feb 2022 at 10:57, Marc Zyngier <maz@kernel.org> wrote: > > On 2022-02-18 21:55, Barry Song wrote: > > dsb(ishst) should be enough here as we only need to guarantee the > > visibility of data to other CPUs in smp inner domain before we > > send the ipi. > > > > Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> > > --- > > drivers/irqchip/irq-gic-v3.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3.c > > b/drivers/irqchip/irq-gic-v3.c > > index 5e935d97207d..0efe1a9a9f3b 100644 > > --- a/drivers/irqchip/irq-gic-v3.c > > +++ b/drivers/irqchip/irq-gic-v3.c > > @@ -1211,7 +1211,7 @@ static void gic_ipi_send_mask(struct irq_data > > *d, const struct cpumask *mask) > > * Ensure that stores to Normal memory are visible to the > > * other CPUs before issuing the IPI. > > */ > > - wmb(); > > + dsb(ishst); > > > > for_each_cpu(cpu, mask) { > > u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); > > I'm not opposed to that change, but I'm pretty curious whether this > makes > any visible difference in practice. Could you measure the effect of this > change > for any sort of IPI heavy workload? >
Does this have to be a DSB ?
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