Messages in this thread | | | Date | Sun, 20 Feb 2022 15:04:18 +0000 | From | "Russell King (Oracle)" <> | Subject | Re: [PATCH] irqchip/gic-v3: use dsb(ishst) to synchronize data to smp before issuing ipi |
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On Sat, Feb 19, 2022 at 05:55:49AM +0800, Barry Song wrote: > dsb(ishst) should be enough here as we only need to guarantee the > visibility of data to other CPUs in smp inner domain before we > send the ipi. > > Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> > --- > drivers/irqchip/irq-gic-v3.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 5e935d97207d..0efe1a9a9f3b 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -1211,7 +1211,7 @@ static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) > * Ensure that stores to Normal memory are visible to the > * other CPUs before issuing the IPI. > */ > - wmb(); > + dsb(ishst);
On ARM, wmb() is a dsb(st) followed by other operations which may include a sync operation at the L2 cache, and SoC specific barriers for the bus. Hopefully, nothing will break if the sledge hammer is replaced by the tack hammer.
-- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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