Messages in this thread | | | Date | Wed, 16 Feb 2022 15:47:33 +0800 | Subject | Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register | From | Like Xu <> |
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On 12/2/2022 4:39 pm, Jim Mattson wrote: >> - pmu->reserved_bits = 0xffffffff00200000ull; >> + pmu->reserved_bits = 0xfffffff000280000ull; > Bits 40 and 41 are guest mode and host mode. They cannot be reserved > if the guest supports nested SVM. >
Indeed, we need (some hands) to do more pmu tests on nested SVM.
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