lkml.org 
[lkml]   [2022]   [Feb]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
SubjectRe: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register
From
On 12/2/2022 4:39 pm, Jim Mattson wrote:
>> - pmu->reserved_bits = 0xffffffff00200000ull;
>> + pmu->reserved_bits = 0xfffffff000280000ull;
> Bits 40 and 41 are guest mode and host mode. They cannot be reserved
> if the guest supports nested SVM.
>

Indeed, we need (some hands) to do more pmu tests on nested SVM.

\
 
 \ /
  Last update: 2022-02-16 08:49    [W:0.088 / U:0.696 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site