Messages in this thread | | | Date | Thu, 18 Nov 2021 15:43:25 +0100 | Subject | Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register | From | Paolo Bonzini <> |
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On 11/18/21 14:03, Like Xu wrote: > From: Like Xu <likexu@tencent.com> > > If we run the following perf command in an AMD Milan guest: > > perf stat \ > -e cpu/event=0x1d0/ \ > -e cpu/event=0x1c7/ \ > -e cpu/umask=0x1f,event=0x18e/ \ > -e cpu/umask=0x7,event=0x18e/ \ > -e cpu/umask=0x18,event=0x18e/ \ > ./workload > > dmesg will report a #GP warning from an unchecked MSR access > error on MSR_F15H_PERF_CTLx. > > This is because according to APM (Revision: 4.03) Figure 13-7, > the bits [35:32] of AMD PerfEvtSeln register is a part of the > event select encoding, which extends the EVENT_SELECT field > from 8 bits to 12 bits. > > Opportunistically update pmu->reserved_bits for reserved bit 19. > > Reported-by: Jim Mattson <jmattson@google.com> > Fixes: ca724305a2b0 ("KVM: x86/vPMU: Implement AMD vPMU code for KVM") > Signed-off-by: Like Xu <likexu@tencent.com> > --- > arch/x86/kvm/svm/pmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c > index 871c426ec389..b4095dfeeee6 100644 > --- a/arch/x86/kvm/svm/pmu.c > +++ b/arch/x86/kvm/svm/pmu.c > @@ -281,7 +281,7 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) > pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; > > pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; > - pmu->reserved_bits = 0xffffffff00200000ull; > + pmu->reserved_bits = 0xfffffff000280000ull; > pmu->version = 1; > /* not applicable to AMD; but clean them to prevent any fall out */ > pmu->counter_bitmask[KVM_PMC_FIXED] = 0; >
Queued, thanks.
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