Messages in this thread | | | Date | Thu, 8 Dec 2022 01:39:51 +0200 | Subject | Re: [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog | From | Dmitry Baryshkov <> |
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On 05/12/2022 18:37, Robert Foss wrote: > Add compatibility for SM8350 display subsystem, including > required entries in DPU hw catalog. > > Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Minor nit below.
> --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > 2 files changed, 197 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 4dac90ee5b8a..ba26af73be53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -112,6 +112,15 @@ > BIT(MDP_INTF3_INTR) | \ > BIT(MDP_INTF4_INTR)) > > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + 0) > + > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_caps sm8350_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0xb, > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 4096, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sm8450_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0xb, > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sm8350_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = 0, > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
Missing ubwc_swizzle. I'll probably fix it as a followup or when applying the patch.
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2ac, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2b4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2bc, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2c4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2ac, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2b4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2bc, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2c4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > + .reg_off = 0x2bc, .bit_off = 20}, > + }, > +}; > +
>
-- With best wishes Dmitry
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