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SubjectRe: [PATCH v3 3/3] arm64: dts: qcom: sm6350: Use specific qmpphy compatible
On Wed, Nov 30, 2022 at 09:14:29AM +0100, Luca Weiss wrote:
> The sc7180 phy compatible works fine for some cases, but it turns out
> sm6350 does need proper phy configuration in the driver, so use the
> newly added sm6350 compatible.
>
> Because the sm6350 compatible is using the new binding, we need to
> change the node quite a bit to match it.
>
> This fixes qmpphy init when no USB cable is plugged in during bootloader
> stage.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Rebase on https://lore.kernel.org/all/20221111094729.11842-2-johan+linaro@kernel.org/
> While this commit deletes the changes there it's still good to get it
> in for completeness
> * Fix clocks, add power-domain
>
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 50 ++++++++--------------------
> 1 file changed, 14 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 43324bf291c3..cb48f03a6cc9 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interconnect/qcom,sm6350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> @@ -1119,49 +1120,26 @@ usb_1_hsphy: phy@88e3000 {
> resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> };
>
> - usb_1_qmpphy: phy@88e9000 {
> - compatible = "qcom,sc7180-qmp-usb3-dp-phy";
> - reg = <0 0x088e9000 0 0x200>,
> - <0 0x088e8000 0 0x40>,
> - <0 0x088ea000 0 0x200>;
> - status = "disabled";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> + usb_1_qmpphy: phy@88e8000 {
> + compatible = "qcom,sm6350-qmp-usb3-dp-phy";
> + reg = <0 0x088e8000 0 0x3000>;
>
> clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> - <&xo_board>,
> - <&rpmhcc RPMH_QLINK_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux", "ref", "com_aux", "usb3_pipe";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
>
> resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> <&gcc GCC_USB3_PHY_PRIM_BCR>;

These have been switched too.

> reset-names = "phy", "common";
>
> - usb_1_ssphy: usb3-phy@88e9200 {
> - reg = <0 0x088e9200 0 0x200>,
> - <0 0x088e9400 0 0x200>,
> - <0 0x088e9c00 0 0x400>,
> - <0 0x088e9600 0 0x200>,
> - <0 0x088e9800 0 0x200>,
> - <0 0x088e9a00 0 0x100>;
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> - clock-names = "pipe0";
> - clock-output-names = "usb3_phy_pipe_clk_src";
> - };
> + #clock-cells = <1>;
> + #phy-cells = <1>;
>
> - dp_phy: dp-phy@88ea200 {
> - reg = <0 0x088ea200 0 0x200>,
> - <0 0x088ea400 0 0x200>,
> - <0 0x088eaa00 0 0x200>,
> - <0 0x088ea600 0 0x200>,
> - <0 0x088ea800 0 0x200>;
> - #phy-cells = <0>;
> - #clock-cells = <1>;
> - };
> + status = "disabled";
> };
>
> dc_noc: interconnect@9160000 {
> @@ -1235,7 +1213,7 @@ usb_1_dwc3: usb@a600000 {
> snps,dis_enblslpm_quirk;
> snps,has-lpm-erratum;
> snps,hird-threshold = /bits/ 8 <0x10>;
> - phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
> phy-names = "usb2-phy", "usb3-phy";
> };
> };

Looks good otherwise. With the resets fixed you can add my:

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

Johan

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