Messages in this thread Patch in this message | | | From | Jia Jie Ho <> | Subject | [PATCH 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2 | Date | Wed, 21 Dec 2022 17:08:19 +0800 |
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Adding StarFive TRNG controller node to VisionFive 2 SoC.
Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4ac159d79d66..dd3ad19772a5 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -455,5 +455,16 @@ uart5: serial@12020000 { reg-shift = <2>; status = "disabled"; }; + + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; + interrupts = <30>; + status = "okay"; + }; }; }; -- 2.25.1
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