Messages in this thread | | | From | JiaJie Ho <> | Subject | RE: [PATCH 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2 | Date | Thu, 22 Dec 2022 08:11:16 +0000 |
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> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Wednesday, December 21, 2022 5:48 PM > To: JiaJie Ho <jiajie.ho@starfivetech.com>; Olivia Mackall > <olivia@selenic.com>; Herbert Xu <herbert@gondor.apana.org.au>; Rob > Herring <robh+dt@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@linaro.org> > Cc: Emil Renner Berthing <kernel@esmil.dk>; Conor Dooley > <conor.dooley@microchip.com>; linux-crypto@vger.kernel.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux- > riscv@lists.infradead.org > Subject: Re: [PATCH 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2 > > > + > > + rng: rng@1600c000 { > > + compatible = "starfive,jh7110-trng"; > > + reg = <0x0 0x1600C000 0x0 0x4000>; > > + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, > > + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; > > + clock-names = "hclk", "ahb"; > > + resets = <&stgcrg > JH7110_STGRST_SEC_TOP_HRESETN>; > > + interrupts = <30>; > > + status = "okay"; > > Drop. It's by default. > I'll fix this in v2.
Thanks, Jia Jie
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