Messages in this thread | | | Date | Tue, 8 Nov 2022 18:18:29 -0800 | From | Pawan Gupta <> | Subject | Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG enumeration |
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On Wed, Nov 09, 2022 at 12:10:32AM +0100, Borislav Petkov wrote: >On Tue, Nov 08, 2022 at 02:51:41PM -0800, Pawan Gupta wrote: >> Looking at bsp_init_amd() this feature bit will only be set on AMD >> families 0x15-0x17. Andrew mentioned that the MSR LS_CFG is present on >> AMD family >= 0x10 && family <= 0x18. > >Do you need to save that MSR on those families? > >Or do 0x15-0x18 suffice? > >Yes, 0x18 because that's Hygon and that does its own detection. > >So, do you need to save it on families 0x10-0x14?
As per Andrew's comment [1] the MSR needs to be restored for dispatch serialising bit(except for family 0x11) :
AMD LS_CFG is more complicated, because the dispatch serialising bit needs setting unilaterally (families 0x10, 0x12 thru 0x18), but the SSBD control ought to resolve on the next context switch.
[1] https://lore.kernel.org/lkml/6049e5bc-122f-5b4c-c1dc-0591eccf3525@citrix.com/
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