Messages in this thread | | | From | Andrew Cooper <> | Subject | Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG enumeration | Date | Wed, 9 Nov 2022 00:45:58 +0000 |
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On 08/11/2022 23:10, Borislav Petkov wrote: > On Tue, Nov 08, 2022 at 02:51:41PM -0800, Pawan Gupta wrote: >> Looking at bsp_init_amd() this feature bit will only be set on AMD >> families 0x15-0x17. Andrew mentioned that the MSR LS_CFG is present on >> AMD family >= 0x10 && family <= 0x18. > Do you need to save that MSR on those families? > > Or do 0x15-0x18 suffice? > > Yes, 0x18 because that's Hygon and that does its own detection. > > So, do you need to save it on families 0x10-0x14?
https://www.amd.com/system/files/documents/software-techniques-for-managing-speculation.pdf Mitigation G-2.
The MSR exists on Fam 10/12/14/15/16/17, and in all cases the LFENCE_DISPATCH bit wants setting if not already set.
The MSR is missing on Fam 0f/11 but these parts already have the wanted behaviour.
~Andrew
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