Messages in this thread | | | Date | Tue, 8 Nov 2022 14:06:33 -0800 | From | Pawan Gupta <> | Subject | Re: [PATCH 1/3] x86/tsx: Add feature bit for TSX control MSR support |
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On Tue, Nov 08, 2022 at 10:27:56AM -0800, Dave Hansen wrote: >On 9/12/22 16:39, Pawan Gupta wrote: >> Support for TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES. >> This is different from how other CPU features are enumerated i.e. via >> CPUID. Enumerating support for TSX control currently has an overhead of >> reading the MSR every time which can be avoided. > >I only see tsx_ctrl_is_supported() getting called in three places: > >> 1 tsx.c tsx_clear_cpuid 138 } else if (tsx_ctrl_is_supported()) { >> 2 tsx.c tsx_dev_mode_disable 161 if (!boot_cpu_has_bug(X86_BUG_TAA) || !tsx_ctrl_is_supported() || >> 3 tsx.c tsx_init 194 if (!tsx_ctrl_is_supported()) { > >Those all look like boot-time things to me.
Except tsx_clear_cpuid() could be called during S3 resume as part of secondary CPU's init, but still its not too often.
>Why does the overhead matter?
This patch is mainly needed for patch 3/3 that relies on feature bits to decide which MSRs to save/restore during suspend/resume.
I just gave a hint about it in the commit message:
This will also be useful for any code that wants to use the feature bit instead of a calling tsx_ctrl_is_supported().
I will fix the commit message with this as the main reason for adding the feature bit.
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