Messages in this thread | | | Date | Thu, 17 Nov 2022 19:46:33 +0100 | From | Robert Richter <> | Subject | Re: [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) |
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On 15.11.22 10:08:51, Dan Williams wrote: > Robert Richter wrote: > > On 14.11.22 16:07:58, Dan Williams wrote: > > > Robert Richter wrote: > > > > When an endpoint is found, all ports in beetween the endpoint and the > > > > CXL host bridge need to be created. In the RCH case there are no ports > > > > in between a host bridge and the endpoint. Skip the enumeration of > > > > intermediate ports. > > > > > > > > The port enumeration does not only create all ports, it also > > > > initializes the endpoint chain by adding the endpoint to every > > > > downstream port up to the root bridge. This must be done also in RCD > > > > mode, but is much more simple as the endpoint only needs to be added > > > > to the host bridge's dport. > > > > > > > > Note: For endpoint removal the cxl_detach_ep() is not needed as it is > > > > released in cxl_port_release(). > > > > > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > > > --- > > > > drivers/cxl/core/port.c | 18 ++++++++++++++++-- > > > > 1 file changed, 16 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > > > > index d10c3580719b..e21a9c3fe4da 100644 > > > > --- a/drivers/cxl/core/port.c > > > > +++ b/drivers/cxl/core/port.c > > > > @@ -1366,8 +1366,24 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) > > > > { > > > > struct device *dev = &cxlmd->dev; > > > > struct device *iter; > > > > + struct cxl_dport *dport; > > > > + struct cxl_port *port; > > > > int rc; > > > > > > > > + /* > > > > + * Skip intermediate port enumeration in the RCH case, there > > > > + * are no ports in between a host bridge and an endpoint. Only > > > > + * initialize the EP chain. > > > > + */ > > > > + if (is_cxl_restricted(cxlmd)) { > > > > > > I changed this to: > > > > > > if (cxlmd->cxlds->rcd) { > > > > I a mail to Bjorn I suggested to have cxl_dev_cap and a cxl_port_cap > > in the pci_dev struct that could be looked up too including RCD mode. > > Checking the pci_dev looks more reasonable to me here, though we could > > have a flag of it in cxlds too. > > Would that not need the PCI core to understand how to walk the RCRB > generically? As far as I understand the RCRB association is ACPI.CEDT > specific.
I am thinking of doing some sort of cxl_setup_pci_dev(pdev) in cxl_pci_probe() which extracts the caps and writes them into a struct pci_dev. Possibly the CXL 68B Flit and VH Capable/Enable bit could be used for RCD mode. But if that is not feasible for some reason a flag somewhere could work too.
-Robert
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