lkml.org 
[lkml]   [2022]   [Nov]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
SubjectRe: [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes
From


On 16/11/2022 13:51, Abel Vesa wrote:
> Add UFS host controller and PHY nodes.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 ++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 07ba709ca35f..27ce382cb594 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1372,6 +1372,82 @@ mmss_noc: interconnect@1780000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,sm8550-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x200>;

> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
These three can go at the bottom.


> + clock-names = "ref", "qref";
> + clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsr TCSR_UFS_CLKREF_EN>;
> +
> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + status = "disabled";
> +
> + ufs_mem_phy_lanes: phy@1d80400 {
> + reg = <0x0 0x01d81000 0x0 0x134>,
> + <0x0 0x01d81200 0x0 0x3d8>,
> + <0x0 0x01d80400 0x0 0x258>,
> + <0x0 0x01d81800 0x0 0x134>,
> + <0x0 0x01d81a00 0x0 0x3d8>;
> + #phy-cells = <0>;
> + };
> + };
> +
> + ufs_mem_hc: ufshc@1d84000 {
> + compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy_lanes>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <2>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc UFS_PHY_GDSC>;
> +
> + iommus = <&apps_smmu 0x60 0x0>;
> +
> + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
> +
> + interconnect-names = "ufs-ddr", "cpu-ufs";
> + clock-names =
Why break the line before adding any entries?

Konrad
> + "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + clocks =
> + <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_LN_BB_CLK3>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + freq-table-hz =
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <75000000 300000000>,
> + <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x0 0x01f40000 0x0 0x20000>;

\
 
 \ /
  Last update: 2022-11-16 13:59    [W:0.165 / U:0.020 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site