Messages in this thread Patch in this message | | | From | LeoLiu-oc <> | Subject | [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge | Date | Tue, 15 Nov 2022 11:12:44 +0800 |
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From: leoliu-oc <leoliu-oc@zhaoxin.com>
Define secondary uncorrectable error mask register, secondary uncorrectable error severity register and secondary error capabilities and control register bits in AER capability for PCIe to PCI/PCI-X Bridge. Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4.
Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com> --- include/uapi/linux/pci_regs.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..37f3baa336d7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -799,6 +799,11 @@ #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ +/* PCIe advanced error reporting extended capabilities for PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ + /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ -- 2.20.1
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