Messages in this thread | | | From | matthew.gerlach@linux ... | Subject | [PATCH v3 0/4] Enhance definition of DFH and use enhancements for uart driver | Date | Tue, 4 Oct 2022 07:37:14 -0700 |
| |
From: Matthew Gerlach <matthew.gerlach@intel.com>
This patchset enhances the definition of the Device Feature Header (DFH) used by the Device Feature List (DFL) bus and then uses the new enhancements in a uart driver.
Patch 1 updates the DFL documentation to provide the motivation behind the enhancements to the definition of the DFH.
Patch 2 adds the definitions for DFHv1.
Patch 3 adds basic support DFHv1. It provides a generic mechanism for describing MSIX interrupts used by a particular feature instance, and it gets the location and size of the feature's register set from DFHv1.
Patch 4 adds a DFL uart driver that makes use of the new features of DFHv1.
Basheer Ahmed Muddebihal (1): fpga: dfl: Add DFHv1 Register Definitions
Matthew Gerlach (3): Documentation: fpga: dfl: Add documentation for DFHv1 fpga: dfl: add basic support for DFHv1 tty: serial: 8250: add DFL bus driver for Altera 16550.
Documentation/fpga/dfl.rst | 49 ++++++++ drivers/fpga/dfl.c | 150 +++++++++++++++++------- drivers/fpga/dfl.h | 36 +++++- drivers/tty/serial/8250/8250_dfl.c | 177 +++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 9 ++ drivers/tty/serial/8250/Makefile | 1 + include/linux/dfl.h | 33 +++++- 7 files changed, 414 insertions(+), 41 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_dfl.c
-- 2.25.1
| |