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SubjectRe: [PATCH 03/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode
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On 29/10/2022 17:16, Manivannan Sadhasivam wrote:
> Add separate tables_hs_g4 instance to allow the PHY driver to configure the
> PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and
> PCS register setting in tables_hs_g4 and the UFS driver can request the
> Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

(Especially if changed to qmp_ufs_init_registers()).

> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 4c6a2b5afc9a..5f2a012707b7 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -553,6 +553,8 @@ struct qmp_phy_cfg {
> const struct qmp_phy_cfg_tables tables;
> /* Additional sequence for HS Series B */
> const struct qmp_phy_cfg_tables tables_hs_b;
> + /* Additional sequence for HS G4 */
> + const struct qmp_phy_cfg_tables tables_hs_g4;
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -587,6 +589,7 @@ struct qmp_phy_cfg {
> * @pcs_misc: iomapped memory space for lane's pcs_misc
> * @qmp: QMP phy to which this lane belongs
> * @mode: PHY mode configured by the UFS driver
> + * @submode: PHY submode configured by the UFS driver
> */
> struct qmp_phy {
> struct phy *phy;
> @@ -600,6 +603,7 @@ struct qmp_phy {
> void __iomem *pcs_misc;
> struct qcom_qmp *qmp;
> u32 mode;
> + u32 submode;
> };
>
> /**
> @@ -993,8 +997,12 @@ static int qmp_ufs_power_on(struct phy *phy)
> qmp_ufs_serdes_init(qphy, &cfg->tables_hs_b);
>
> qmp_ufs_lanes_init(qphy, &cfg->tables);
> + if (qphy->submode == UFS_HS_G4)
> + qmp_ufs_lanes_init(qphy, &cfg->tables_hs_g4);
>
> qmp_ufs_pcs_init(qphy, &cfg->tables);
> + if (qphy->submode == UFS_HS_G4)
> + qmp_ufs_pcs_init(qphy, &cfg->tables_hs_g4);
>
> ret = reset_control_deassert(qmp->ufs_reset);
> if (ret)
> @@ -1083,6 +1091,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> struct qmp_phy *qphy = phy_get_drvdata(phy);
>
> qphy->mode = mode;
> + qphy->submode = submode;
>
> return 0;
> }

--
With best wishes
Dmitry

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