Messages in this thread | | | From | Krzysztof Kozlowski <> | Subject | Re: [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents | Date | Tue, 18 Oct 2022 09:19:12 -0400 |
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On Thu, 13 Oct 2022 17:13:40 +0200, David Virag wrote: > "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by > 2 to achieve a by 4 division, thus their parents are the respective > "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents. > This leads to the kernel thinking "div4"s and everything under them run > at 2x the clock speed. Fix this. > > > [...]
Applied, thanks!
[1/1] clk: samsung: exynos7885: Correct "div4" clock parents https://git.kernel.org/krzk/linux/c/ef80c95c29dc67c3034f32d93c41e2ede398e387
Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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