Messages in this thread | | | Date | Thu, 13 Oct 2022 10:35:54 -0400 | Subject | Re: [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents | From | Krzysztof Kozlowski <> |
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On 13/10/2022 11:13, David Virag wrote: > "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by > 2 to achieve a by 4 division, thus their parents are the respective > "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents. > This leads to the kernel thinking "div4"s and everything under them run > at 2x the clock speed. Fix this. > > Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver") > Signed-off-by: David Virag <virag.david003@gmail.com> > ---
Looks good, I'll take it after merge window.
Best regards, Krzysztof
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