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SubjectRe: [PATCH v10, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data
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Hi, Yongqiang:

On Mon, 2022-10-10 at 16:50 +0800, Yongqiang Niu wrote:
> if gce work control by software, we need set software enable
> for MT8186 Soc
>
> there is a handshake flow between gce and ddr hardware,
> if not set ddr enable flag of gce, ddr will fall into idle
> mode, then gce instructions will not process done.
> we need set this flag of gce to tell ddr when gce is idle or busy
> controlled by software flow.
>
> 0x48[2:0] means control by software
> 0x48[18:16] means ddr enable
> 0x48[2:0] is pre-condition of 0x48[18:16].
> if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
> time.
> and only these bits is useful, other bits is useless bits

Reviewed-by: CK Hu <ck.hu@mediatek.com>

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index c3cb24f51699..d2363c6b8b7a 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -39,6 +39,7 @@
>
> #define GCE_GCTL_VALUE 0x48
> #define GCE_CTRL_BY_SW GENMASK(2, 0)
> +#define GCE_DDR_EN GENMASK(18, 16)
>
> #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
> #define CMDQ_THR_ENABLED 0x1
> @@ -81,6 +82,7 @@ struct cmdq {
> bool suspended;
> u8 shift_pa;
> bool control_by_sw;
> + bool sw_ddr_en;
> u32 gce_num;
> };
>
> @@ -88,6 +90,7 @@ struct gce_plat {
> u32 thread_nr;
> u8 shift;
> bool control_by_sw;
> + bool sw_ddr_en;
> u32 gce_num;
> };
>
> @@ -127,10 +130,16 @@ static void cmdq_thread_resume(struct
> cmdq_thread *thread)
> static void cmdq_init(struct cmdq *cmdq)
> {
> int i;
> + u32 gctl_regval = 0;
>
> WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> if (cmdq->control_by_sw)
> - writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> + gctl_regval = GCE_CTRL_BY_SW;
> + if (cmdq->sw_ddr_en)
> + gctl_regval |= GCE_DDR_EN;
> +
> + if (gctl_regval)
> + writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE);
>
> writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> CMDQ_THR_SLOT_CYCLES);
> for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> @@ -545,6 +554,7 @@ static int cmdq_probe(struct platform_device
> *pdev)
> cmdq->thread_nr = plat_data->thread_nr;
> cmdq->shift_pa = plat_data->shift;
> cmdq->control_by_sw = plat_data->control_by_sw;
> + cmdq->sw_ddr_en = plat_data->sw_ddr_en;
> cmdq->gce_num = plat_data->gce_num;
> cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> IRQF_SHARED,
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