Messages in this thread Patch in this message | | | From | Rishabh Agrawal <> | Subject | [PATCH v2] Add hardcoded crystal clock for KabyLake | Date | Tue, 18 Oct 2022 19:01:32 +0000 |
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Set KabyLake crystal clock manually since the TSC calibration is off by 0.5%. All the tests that are based on the timer/clock will fail in this case.
The HPET has been disabled by upstream due to PC10 issue causing the 3 hatch devices, dratini, jinlon, and kohaku to not calibrate the clock precisely. These 3 devices are KabyLake devices. Intel team has verified that all KBL devices have 24.0 MHz clock frequency, therefore this change is valid.
Signed-off-by: Rishabh Agrawal <rishabhagr@chromium.org> ---
Changes in v2: - Adding Thomas Gleixner, Daniel Drake, Rafael Wysocki, Len brown and Ingo to review since you worked on this.
arch/x86/kernel/tsc.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index cafacb2e58cc..63a06224fa48 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -644,10 +644,21 @@ unsigned long native_calibrate_tsc(void) * Denverton SoCs don't report crystal clock, and also don't support * CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal * clock. + * + * Intel KabyLake devices' clocks are off by 0.5% when using the below + * calculation, so hardcode 24.0 MHz crystal clock. */ - if (crystal_khz == 0 && - boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT_D) - crystal_khz = 25000; + if (crystal_khz == 0) { + switch (boot_cpu_data.x86_model) { + case INTEL_FAM6_ATOM_GOLDMONT_D: + crystal_khz = 25000; + break; + case INTEL_FAM6_KABYLAKE_L: + crystal_khz = 24000; + break; + } + + } /* * TSC frequency reported directly by CPUID is a "hardware reported" -- 2.38.0.413.g74048e4d9e-goog
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