Messages in this thread | | | From | Heiko Stuebner <> | Subject | [PATCH v6 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores | Date | Wed, 12 Oct 2022 01:18:39 +0200 |
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The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension but not completely identical, so this series
changes in v6: - follow Anup's suggestion and hook into the (pending) cpuinfo patch [2] instead of modifying the core sbi_get_* functions
changes in v5: - add received Reviews - fix sbi caching wrt. negative values (Drew) - add comment about specific c9xx arch- and imp-ids (Conor)
changes in v4: - add new patch to cache sbi mvendor, march and mimp-ids (Atish) - errata dependencies in one line (Conor) - make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish)
changes in v3: - improve commit message (Atish, Conor) - IS_ENABLED and BIT() in errata probe (Conor)
The change depends on my cpufeature/t-head errata probe cleanup series [1].
changes in v2: - use alternatives for the CSR access - make the irq num selection a bit nicer
There is of course a matching opensbi-part whose most recent implementation can be found on [0].
[0] https://patchwork.ozlabs.org/project/opensbi/cover/20221004164227.1381825-1-heiko@sntech.de [1] https://lore.kernel.org/all/20220905111027.2463297-1-heiko@sntech.de/ [2] https://lore.kernel.org/r/20220727043829.151794-1-apatel@ventanamicro.com
Heiko Stuebner (2): RISC-V: Cache SBI vendor values drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores
arch/riscv/Kconfig.erratas | 13 +++++++++++ arch/riscv/errata/thead/errata.c | 19 ++++++++++++++++ arch/riscv/include/asm/errata_list.h | 16 ++++++++++++- arch/riscv/include/asm/sbi.h | 5 ++++ arch/riscv/kernel/cpu.c | 30 +++++++++++++++++++++--- drivers/perf/riscv_pmu_sbi.c | 34 ++++++++++++++++++++-------- 6 files changed, 103 insertions(+), 14 deletions(-)
-- 2.35.1
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