Messages in this thread Patch in this message | | | From | Mans Rullgard <> | Subject | [PATCH] ARM: dts: sunxi: h3/h5: add r_uart node | Date | Wed, 12 Jan 2022 17:33:27 +0000 |
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There is an additional UART in the PL I/O block. Add a node and pinmux for it.
Signed-off-by: Mans Rullgard <mans@mansr.com> --- The "documentation" doesn't mention any DMA channels for this UART. If it nonetheless does have DMA capability and someone knows the channel assignments, feel free to amend. --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 22d533d18992..55ffba5a4e9f 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -884,6 +884,19 @@ r_i2c: i2c@1f02400 { #size-cells = <0>; }; + r_uart: serial@1f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_APB0_UART>; + resets = <&r_ccu RST_APB0_UART>; + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -909,6 +922,11 @@ r_pwm_pin: r-pwm-pin { pins = "PL10"; function = "s_pwm"; }; + + r_uart_pins: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; }; r_pwm: pwm@1f03800 { -- 2.34.1
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