Messages in this thread | | | From | Stephen Boyd <> | Date | Mon, 13 Sep 2021 12:57:50 -0700 | Subject | Re: [PATCH V3 1/2] pinctrl: qcom: spmi-gpio: correct parent irqspec translation |
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Quoting satya priya (2021-09-08 23:01:27) > From: David Collins <collinsd@codeaurora.org> > > pmic_gpio_child_to_parent_hwirq() and > gpiochip_populate_parent_fwspec_fourcell() translate a pinctrl- > spmi-gpio irqspec to an SPMI controller irqspec. When they do > this, they use a fixed SPMI slave ID of 0 and a fixed GPIO > peripheral offset of 0xC0 (corresponding to SPMI address 0xC000). > This translation results in an incorrect irqspec for secondary > PMICs that don't have a slave ID of 0 as well as for PMIC chips > which have GPIO peripherals located at a base address other than > 0xC000. > > Correct this issue by passing the slave ID of the pinctrl-spmi- > gpio device's parent in the SPMI controller irqspec and by > calculating the peripheral ID base from the device tree 'reg' > property of the pinctrl-spmi-gpio device. > > Signed-off-by: David Collins <collinsd@codeaurora.org> > Signed-off-by: satya priya <skakit@codeaurora.org> > Fixes: ca69e2d165eb ("qcom: spmi-gpio: add support for hierarchical IRQ chip") > ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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