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Subject[mark-rutland:arm64/head/cleanup 13/14] arch/arm64/kernel/head.S:321: Error: too many positional arguments
tree:   https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git arm64/head/cleanup
head: 2fca07d7b5e0a0dc3fb5bdec5f470411d57a4551
commit: a0b6ee23fbe0b8bb87c01ff990c3a1e0c99e691b [13/14] arm64: head: refactor `create_table_entry`
config: arm64-randconfig-s032-20210806 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 10.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-348-gf0e6938b-dirty
# https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/commit/?id=a0b6ee23fbe0b8bb87c01ff990c3a1e0c99e691b
git remote add mark-rutland https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
git fetch --no-tags mark-rutland arm64/head/cleanup
git checkout a0b6ee23fbe0b8bb87c01ff990c3a1e0c99e691b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=arm64 SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

arch/arm64/kernel/head.S: Assembler messages:
>> arch/arm64/kernel/head.S:321: Error: too many positional arguments


vim +321 arch/arm64/kernel/head.S

308
309 /*
310 * If VA_BITS < 48, we have to configure an additional table level.
311 * First, we have to verify our assumption that the current value of
312 * VA_BITS was chosen such that all translation levels are fully
313 * utilised, and that lowering T0SZ will always result in an additional
314 * translation level to be configured.
315 */
316 #if VA_BITS != EXTRA_SHIFT
317 #error "Mismatch between VA_BITS and page size/number of translation levels"
318 #endif
319 mov x4, EXTRA_PTRS
320 add x1, x0, #PAGE_SIZE
> 321 write_pte_offset x0, x1, PMD_TYPE_TABLE, x1, EXTRA_SHIFT, EXTRA_PTRS, x5, x6, x7
322 add x0, x0, #PAGE_SIZE
323 #else
324 /*
325 * If VA_BITS == 48, we don't have to configure an additional
326 * translation level, but the top-level table has more entries.
327 */
328 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
329 str_l x4, idmap_ptrs_per_pgd, x5
330 #endif
331 1:
332 ldr_l x4, idmap_ptrs_per_pgd
333 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
334 mov x7, SWAPPER_MM_MMUFLAGS
335
336 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
337
338 /*
339 * Since the page tables have been populated with non-cacheable
340 * accesses (MMU disabled), invalidate those tables again to
341 * remove any speculatively loaded cache lines.
342 */
343 dmb sy
344 adrp x0, idmap_pg_dir
345 adrp x1, idmap_pg_end
346 bl dcache_inval_poc
347
348 ret x28
349 SYM_FUNC_END(__create_idmap_tables)
350

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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