Messages in this thread Patch in this message | | | Date | Fri, 20 Aug 2021 13:34:43 -0000 | From | "irqchip-bot for Chen-Yu Tsai" <> | Subject | [irqchip: irq/irqchip-next] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used |
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The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: 2341aaa8fa8f8f6be550e6c4d4c1ce4283d15ea9 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/2341aaa8fa8f8f6be550e6c4d4c1ce4283d15ea9 Author: Chen-Yu Tsai <wenst@chromium.org> AuthorDate: Thu, 12 Aug 2021 01:15:05 +08:00 Committer: Marc Zyngier <maz@kernel.org> CommitterDate: Fri, 20 Aug 2021 14:32:40 +01:00
irqchip/gic-v3: Fix priority comparison when non-secure priorities are used
When non-secure priorities are used, compared to the raw priority set, the value read back from RPR is also right-shifted by one and the highest bit set.
Add a macro to do the modifications to the raw priority when doing the comparison against the RPR value. This corrects the pseudo-NMI behavior when non-secure priorities in the GIC are used. Tested on 5.10 with the "IPI as pseudo-NMI" series [1] applied on MT8195.
[1] https://lore.kernel.org/linux-arm-kernel/1604317487-14543-1-git-send-email-sumit.garg@linaro.org/
Fixes: 336780590990 ("irqchip/gic-v3: Support pseudo-NMIs when SCR_EL3.FIQ == 0") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210811171505.1502090-1-wenst@chromium.org --- drivers/irqchip/irq-gic-v3.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index e0f4deb..e7a0b55 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -100,6 +100,15 @@ EXPORT_SYMBOL(gic_pmr_sync); DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); EXPORT_SYMBOL(gic_nonsecure_priorities); +#define GICD_INT_RPR_PRI(priority) \ + ({ \ + u32 __priority = (priority); \ + if (static_branch_unlikely(&gic_nonsecure_priorities)) \ + __priority = 0x80 | (__priority >> 1); \ + \ + __priority; \ + }) + /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ static refcount_t *ppi_nmi_refs; @@ -687,7 +696,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs return; if (gic_supports_nmi() && - unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { + unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) { gic_handle_nmi(irqnr, regs); return; }
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