| Date | Fri, 13 Aug 2021 12:47:41 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH Part1 RFC v4 10/36] x86/compressed: Register GHCB memory when SEV-SNP is active |
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On Wed, Jul 07, 2021 at 01:14:40PM -0500, Brijesh Singh wrote: > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index aee07d1bb138..b19d8d301f5d 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -45,6 +45,17 @@ > (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ > (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) > > +/* GHCB GPA Register */ > +#define GHCB_MSR_GPA_REG_REQ 0x012 > +#define GHCB_MSR_GPA_REG_VALUE_POS 12 > +#define GHCB_MSR_GPA_REG_GFN_MASK GENMASK_ULL(51, 0) > +#define GHCB_MSR_GPA_REQ_GFN_VAL(v) \ > + (((unsigned long)((v) & GHCB_MSR_GPA_REG_GFN_MASK) << GHCB_MSR_GPA_REG_VALUE_POS)| \ > + GHCB_MSR_GPA_REG_REQ) > + > +#define GHCB_MSR_GPA_REG_RESP 0x013 > +#define GHCB_MSR_GPA_REG_RESP_VAL(v) ((v) >> GHCB_MSR_GPA_REG_VALUE_POS)
Simplify...
-- Regards/Gruss, Boris.
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