Messages in this thread | | | From | "Tian, Kevin" <> | Subject | RE: Programming PASID in IMS entries | Date | Wed, 7 Jul 2021 23:51:21 +0000 |
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> From: Thomas Gleixner <tglx@linutronix.de> > Sent: Wednesday, July 7, 2021 4:51 PM > > > Also, from a previous discussion [1], we want to make IMS more dynamic: > > > > Given the QEMU behavior it doesn't ask for all IRQs upfront. It only > > allocates 1, and when it unmasks the 2nd, it wants to dynamically add a > > second. This will allow adding a second IRQ without having to free all > > the old irqs and reacquire the new number (as it is done today). > > > > This dynamic behavior is only for MSIx/IMS backed entries. For legacy > > MSI, QEMU will allocate everything upfront. Since it has a > > "num_vectors" enabled, nothing can be dynamically done for MSI. Kevin > > is looking to have this fixed for legacy to stop the dynamic part for > > MSI. We are pursuing this change just for IMS first, and once it > > works, we can replicate the same for MSIx too. > > No. Fix the existing stuff first and then IMS just works. >
Does below sound a plan?
1. Fix Qemu to allocate all possible irqs when guest unmasks MSI/MSI-X, instead of freeing and re-allocating in the fly. This is an improvement for existing kernels which don't support dynamic resize.
2. Extend MSI-X core to support dynamic resize. Via VFIO_IRQ_INFO_ NORESIZE Qemu can enable dynamic resize if the flag is false. and from your comment dev-msi resize will be covered too with this change.
3. Add hypercall (or a pv irqchip) to provide feedback into guest in case of irq shortage. This is also necessary to enable guest ims.
Thanks Kevin
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