Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Fri, 16 Jul 2021 14:49:39 +0200 | Subject | Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC |
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Hi Yash,
On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote: > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > around the SiFIve U7 Core Complex and a TileLink interconnect. > > This file is expected to grow as more device drivers are added to the > kernel. > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
Thanks for your patch, which became commit 57985788158a5a6b ("riscv: dts: add initial support for the SiFive FU740-C000 SoC").
> --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > @@ -0,0 +1,293 @@
> + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + cpu0: cpu@0 { > + compatible = "sifive,bullet0", "riscv";
I'm wondering why you're using
compatible = "sifive,bullet0", "riscv";
According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC"), it should be
compatible = "sifive,u74-mc", "riscv";
instead.
Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using
compatible = "sifive,e51", "sifive,rocket0", "riscv";
and
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
but according to the DT bindings the rocket part should not be present.
Is there any specific reason for that? Should the DT bindings and/or the DTS files be fixed?
Thanks!
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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