Messages in this thread | | | From | Bin Meng <> | Date | Wed, 16 Dec 2020 14:06:07 +0800 | Subject | Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC |
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Hi Yash,
On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> wrote: > > > -----Original Message----- > > From: Bin Meng <bmeng.cn@gmail.com> > > Sent: 10 December 2020 19:05 > > To: Yash Shah <yash.shah@openfive.com> > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > > C000 SoC > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > > > > FU740-C000 Soc > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > This file is expected to grow as more device drivers are added to the > > > kernel. > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > --- > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > +++++++++++++++++++++++++++++ > > > 1 file changed, 293 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > new file mode 100644 > > > index 0000000..eeb4f8c3 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > @@ -0,0 +1,293 @@ > > ... > > > > + plic0: interrupt-controller@c000000 { > > > + #interrupt-cells = <1>; > > > + #address-cells = <0>; > > > + compatible = "sifive,fu540-c000-plic", > > > + "sifive,plic-1.0.0"; > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > That's because it is not required. There won't be any difference in driver code for FU740 plic.
Are there any driver changes for the drivers that have an updated fu640-c000-* bindings? I don't see them in the linux-riscv list.
> > ... > > > > + eth0: ethernet@10090000 { > > > + compatible = "sifive,fu540-c000-gem"; > > > > "sifive,fu740-c000-gem"? > > > > Same reason as above. > > Thanks for your review.
Regards, Bin
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