Messages in this thread | | | Date | Tue, 01 Jun 2021 14:47:15 +0200 | From | Michael Walle <> | Subject | Re: [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode |
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Am 2021-05-31 20:17, schrieb Pratyush Yadav: > The Octal DTR configuration is stored in the CFR5V register. This > register is 1 byte wide. But 1 byte long transactions are not allowed > in > 8D-8D-8D mode. Since the next byte address does not contain any > register, it is safe to write any value to it. Write a 0 to it. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > ---
Can't say much, because there is no public datasheet, is there?
But looks sane. Same for patch 3/6.
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