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    SubjectRe: [PATCH v5 28/28] x86/fpu/amx: Clear the AMX state when appropriate
    On Mon, May 24, 2021 at 10:07 AM Dave Hansen <dave.hansen@intel.com> wrote:

    > Could we maybe say:
    >
    > /*
    > * Leaving state in the TILE registers may prevent the
    > * processor from entering low-power idle states. Use
    > * TILERELEASE to initialize the state. Destroying
    > * fpregs state is safe after the fpstate update.
    > */

    Ack

    > Also, referencing fpregs/fpstate is really nice because the codes
    > doesn't actually say "XSAVE" anywhere.
    >
    > > + if (fpu->state_mask & XFEATURE_MASK_XTILE_DATA)
    > > + tile_release();
    >
    > Doesn't this tile_release() need a fpregs_deactivate()? Otherwise, the
    > next XRSTOR might get optimized away because it thinks there's still
    > good data in the fpregs.
    >
    > Will this unnecessarily thwart the modified optimization in cases where
    > we go and run this task again without ever going out to userspace? Will
    > this impact context-switch latency for *EVERY* context switch in order
    > to go to a lower idle state in a few minutes, hours, or never?

    yeah, seems we missed that.


    thanks!
    Len Brown, Intel Open Source Technology Center

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