Messages in this thread | | | From | Peter Geis <> | Date | Fri, 14 May 2021 11:25:35 -0400 | Subject | Re: [PATCH v3] net: phy: add driver for Motorcomm yt8511 phy |
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On Fri, May 14, 2021 at 10:52 AM Andrew Lunn <andrew@lunn.ch> wrote: > > > > I also wonder about bits 15:12 of PHY EXT ODH: Delay and driver > > > strength CFG register. > > > > The default value *works*, and from an emi perspective we want the > > lowest strength single that is reliable. > > I was not meaning signal strength, but Txc_delay_sel_fe, > > selecte tx_clk_rgmii delay in chip which is used to latch txd_rgmii > in 100BT/10BTe mode. 150ps step. Default value 15 means about 2ns > clock delay compared to txd_rgmii in typical cornor. > > [Typos courtesy of the datasheet, not me!] > > This sounds like more RGMII delays. It seems like PHY EXT 0CH is about > 1G mode, and PHY EXT 0DH is about 10/100 mode. I think you probably > need to set this bits as well. Have you tested against a link peer at > 10 Half? 100 Full?
Good Catch!
Guess I'll have to set that too, anything else you'd recommend looking into?
> > Andrew
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