lkml.org 
[lkml]   [2021]   [Apr]   [9]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH 4/4] ARM: dts: Fix-up EMMC2 controller's frequency
From
Date
Hi Nicolas,

Am 09.04.21 um 12:54 schrieb Nicolas Saenz Julienne:
> Hi again,
>
> On Wed, 2021-04-07 at 16:37 -0400, Alan Cooper wrote:
>> Nicolas,
>>
>> I got a better description of the failure and it looks like the bus
>> clock needs to be limited to 300KHz for a 500MHz core clock.
>> What's happening is that an internal reset sequence is needed after a
>> command timeout and the reset signal needs to be asserted for at least
>> 2 ticks of the bus clock. This is done using a 12 bit counter clocked
>> by the core clock. That means a 500MHz core clock produces a 122KHz
>> reset signal which is too fast for 2 ticks of the 200KHz bus clock
>> (100KHz) but is okay for the 300KHz (150Khz) bus clock.
> Is there any value in implementing this in a generic way?

i don't have any idea which callback could manipulate the reset
duration. Limiting the min clk frequency looks like the less invasive
solution to me. Touching the DT isn't recommend.

Best regards



\
 
 \ /
  Last update: 2021-04-09 20:29    [W:0.063 / U:0.256 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site