Messages in this thread | | | Subject | Re: [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM | From | Guenter Roeck <> | Date | Tue, 30 Mar 2021 12:02:17 -0700 |
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On 3/30/21 10:52 AM, Jacob Pan wrote: > Hi Guenter, > > On Mon, 22 Mar 2021 10:53:38 -0700, Guenter Roeck <linux@roeck-us.net> > wrote: > >> On Tue, Mar 02, 2021 at 02:13:57AM -0800, Jacob Pan wrote: >>> Write protect bit, when set, inhibits supervisor writes to the read-only >>> pages. In supervisor shared virtual addressing (SVA), where page tables >>> are shared between CPU and DMA, IOMMU PASID entry WPE bit should match >>> CR0.WP bit in the CPU. >>> This patch sets WPE bit for supervisor PASIDs if CR0.WP is set. >>> >>> Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com> >>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> >>> --- >> >> ia64:defconfig: >> >> drivers/iommu/intel/pasid.c: In function 'pasid_enable_wpe': >> drivers/iommu/intel/pasid.c:536:22: error: implicit declaration of >> function 'read_cr0' drivers/iommu/intel/pasid.c:539:23: error: >> 'X86_CR0_WP' undeclared >> >> Maybe it _is_ time to retire ia64 ? > > Good catch, sorry for the late reply. I guess otherwise I will have to do > some #ifdef? >
I really can't tell you how to resolve this.
> There are many basic x86 helpers are missing in ia64. > I'd say that Intel needs to decide what to do with the ia64 architecture.
Guenter
> +Tony > > Thanks, > > Jacob >
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