Messages in this thread | | | Date | Tue, 30 Mar 2021 10:52:00 -0700 | From | Jacob Pan <> | Subject | Re: [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM |
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Hi Guenter,
On Mon, 22 Mar 2021 10:53:38 -0700, Guenter Roeck <linux@roeck-us.net> wrote:
> On Tue, Mar 02, 2021 at 02:13:57AM -0800, Jacob Pan wrote: > > Write protect bit, when set, inhibits supervisor writes to the read-only > > pages. In supervisor shared virtual addressing (SVA), where page tables > > are shared between CPU and DMA, IOMMU PASID entry WPE bit should match > > CR0.WP bit in the CPU. > > This patch sets WPE bit for supervisor PASIDs if CR0.WP is set. > > > > Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com> > > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> > > --- > > ia64:defconfig: > > drivers/iommu/intel/pasid.c: In function 'pasid_enable_wpe': > drivers/iommu/intel/pasid.c:536:22: error: implicit declaration of > function 'read_cr0' drivers/iommu/intel/pasid.c:539:23: error: > 'X86_CR0_WP' undeclared > > Maybe it _is_ time to retire ia64 ?
Good catch, sorry for the late reply. I guess otherwise I will have to do some #ifdef?
There are many basic x86 helpers are missing in ia64.
+Tony
Thanks,
Jacob
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